1. The Field of the Art.
This invention relates to a dynamic random access memories (DRAMs) and, more particularly, to sensing and refreshing circuitry.
2. Description of the Prior Art.
DRAMS are widely used as memory storage devices. In one transistor memory storage cell DRAMs, data is read into and out from a storage capacitor, through a storage transistor, onto a bit line. A word line turns on the gate of the storage transistor to allow data read in and read out. A plurality of such cells are attached to each bit line.
As the memory storage capabilities of DRAMs have increased, the storage capacitors have become increasingly smaller and the number of one transistor memory cells attached to a single bit line have increased. Thus, there has been a need for more sensitive sensing amplifiers and accompanying refreshing circuitry.
U.S. Pat. No. 4,811,302, for example, uses a pair of sense amplifiers that operate simultaneously to improve the sensitivity of the sensing. Furthermore, during operation, only half of the bit line is attached to the sense amplifiers, thereby further reducing the capacitance of the bit line.
However, there still exists the need for developing sensing and refresh circuitry that reduces the dimensions of the DRAM chip, especially chip length.